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booth_mul
- 一种可以完成16位有符号／无符号二进制数乘法的乘法器。该乘法器采用了改进的Booth算法，简化了部分积的符号扩展，采用Wallace树和超前进位加法器来进一步提高电路的运算速度。本乘法器可以作为嵌入式CPU内核的乘法单元，整个设计用VHDL语言实现。-a 16 to be completed with symbols / unsigned multiplication of the number of binary multipliers. The multiplier used to impr
alu
- 16位RISC CPU的ALU，使用VHDL编写
MyCPU16
- 16位cpu设计VHDL源码，其中包括alu，clock，memory等部分的设计
alu181
- alu运算器vhdl代码，介绍了16中运算方法，可用于cpu的设计中
CPU16
- 用VHDL语言开发的一个16位的具有5级流水线的CPU设计
5744114893829
- 用VHDL实现16位的简单CPU。具有加减乘除等功能-vhdl cpu can do add sub and so on
cpu01
- cpu 16 bit fpga vhdl
cpu16
- 16位cpu设计vhdl源码。主要实现risc机器模型-16-bit cpu design code
c16_latest.tar
- c16 ucore. this a 16 VHDL cpu core. complete with Assembler and C compiler. All src code included.-c16 ucore. this a 16 VHDL cpu core. complete with Assembler and C compiler. All src code included.
vhdl_16CPU
- 16位CPU设计，采用VHDL语言，自带测试汇编语言，能实现基本运算和移位、跳转等操作-16-bit CPU design, using VHDL language, self-test assembly language, to achieve the basic operations and shift operations such as jump
95637012Multiplier
- 一种可以完成16位有符号／无符号二进制数乘法的乘法器。该乘法器采用了改进的booth算法，简化了部分积的符号扩展，采用Wallace树和超前进位加法器来进一步提高电路的运算速度。本乘法器可以作为嵌入式CPU内核的乘法单元，整个设计用VHDL语言实现。- This file contains all the entity-architectures for a complete-- k-bit x k-bit Booth multiplier.-- the design makes use of
altera_inspector.log
- vhdl代码 使用quartus编译 cpu中 alu的设计 可作为课程设计的参考 此为16的运算器-VHDL -code using Quartus compiler cpu in alu design of curriculum design can be used as a reference for this for 16 computing device
091220111singalcpu
- 用verilog HDL语言或者VHDL语言来编写，实现单周期CPU的设计。能够完成以下十六条指定： add rd, rs, rt addu rd, rs, rt addi rt, rs, imm addiu rt, rs, imm sub rd, rs, rt subu rd, rs, rt nor rd, rs, rt xori rt, rs, imm clo clz slt rd, rs, rt sltu rd, rs, rt slti
cpu_store
- VHDL语言制作CPU，8位，16条指令，能够完成多种操作. -VHDL language production CPU, 8-bit, 16 instruction, to complete a variety of operations. VHDL language with CPU, 8-bit, 16 instruction, to complete a variety of operations.
EDAandVHDL3
- 包含本系列的第三部分内容，详细介绍了VHDL状态机的概念及其使用和16位CISC CPU设计。-The third part contains the contents of this series, detailing the concept and its use of 16-bit CISC CPU design and VHDL state machine.